Monolithic low noise and low zero-g offset CMOS/MEMS accelerometer readout scheme

Yu Sian Liu*, Kuei-Ann Wen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/ √ Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.

Original languageEnglish
Article number637
JournalMicromachines
Volume9
Issue number12
DOIs
StatePublished - 30 Nov 2018

Keywords

  • Accelerometer readout
  • Low noise
  • Low zero-g offset

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