Modified polycrystalline silicon chemical-vapor deposition process for improving roughness at oxide/polycrystalline silicon interface

J. J. Chang, Tsung-Eong Hsien, Y. L. Wang*, W. T. Tseng, C. P. Liu, C. Y. Lan

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

A new modified low pressure chemical-vapor deposition process for stacked polysilicon (poly-Si) films is developed in this study. The proposed stacked film process combines polysilicon with amorphous silicon films. In this process, polysilicon film was deposited first at 630° C, followed by a continuous temperature decrease down to 560°C for the deposition of amorphous silicon film. It was found that the doped stacked polysilicon films deposited by this process result in lowering of surface roughness, together with reduction of the (311) phase of the doped amorphous silicon and (110) phase of the doped polysilicon. As a consequence, device performance based on the stacked films also improves. Results of surface roughness analysis indicated that the doped stacked polysilicon film has a root-mean square surface roughness (Rrms) of 78 Å, which is smaller than those of doped conventional (630 °C) polysilicon film (Rrms=97 Å), and doped amorphous silicon film (Rrms=123 Å, deposited at 560°C). Transmission electron microscopic (TEM) observation performed at oxide/polysilicon interface showed that the conventional (630°C) oxide/polysilicon interface has high angle grain boundaries on the polysilicon side, which may induce leakage current around the interfacial area.

Original languageEnglish
Pages (from-to)164-168
Number of pages5
JournalThin Solid Films
Volume472
Issue number1-2
DOIs
StatePublished - 24 Jan 2005

Keywords

  • Annealing
  • Grain boundary
  • Silicon
  • Silicon oxide

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