Modeling the impact of random grain boundary traps on the electrical behavior of vertical gate 3-D NAND flash memory devices

Yi Hsuan Hsiao, Hang Ting Lue, Wei Chen Chen, Kuo Pin Chang, Yen Hao Shih, Bing-Yue Tsui, Kuang Yeu Hsieh, Chih Yuan Lu

Research output: Contribution to journalArticlepeer-review

27 Scopus citations

Abstract

The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control.

Original languageEnglish
Article number6813697
Pages (from-to)2064-2070
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume61
Issue number6
DOIs
StatePublished - 1 Jan 2014

Keywords

  • 3-D NAND Flash
  • grain boundary
  • grain boundary traps
  • poly Si thin-film transistor (TFT)
  • vertical gate (VG).

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