Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

Sourabh Khandelwal, Harshit Agarwal, Juan Pablo Duarte, Kaiman Chan, Sagnik Dey, Yogesh Singh Chauhan, Chen-Ming Hu

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

We enhance the capability of industry standard compact model BSIM6 to model the parasitic current Iedge at the shallow trench isolation edge. Accurate, efficient, and scalable model for Iedge is developed by finding the key differences between Iedge and main device drain current (Imain). It is found that Iedge has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to Imain. These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.

Original languageEnglish
Article number7079473
Pages (from-to)1291-1294
Number of pages4
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume34
Issue number8
DOIs
StatePublished - 1 Aug 2015

Keywords

  • Analog technology
  • BSIM6
  • compact models
  • parasitic currents
  • shallow trench isolation (STI) edge effects

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