The scaling of CMOSFET's is ultimately limited by the short-channel effects such as Vth roll-off and Drain-Induced-Barrier-Lowering (DIBL). In this paper, a unified physical model is presented for short-channel effects in deep-submicron CMOS transistors taking into account the impacts of channel engineering, defect-enhanced diffusion, and polysilicon gate depletion. The model agrees well with experiment data for several CMOS technologies.
|Number of pages||5|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China|
Duration: 3 Jun 1997 → 5 Jun 1997
|Conference||Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications|
|Period||3/06/97 → 5/06/97|