Modeling short-channel effects of CMOSFET's taking account for channel-engineering, defect-enhanced-diffusion and gate-depletion

Bin Yu*, Wen Chin Lee, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

The scaling of CMOSFET's is ultimately limited by the short-channel effects such as Vth roll-off and Drain-Induced-Barrier-Lowering (DIBL). In this paper, a unified physical model is presented for short-channel effects in deep-submicron CMOS transistors taking into account the impacts of channel engineering, defect-enhanced diffusion, and polysilicon gate depletion. The model agrees well with experiment data for several CMOS technologies.

Original languageEnglish
Pages298-302
Number of pages5
StatePublished - 1 Jan 1997
EventProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China
Duration: 3 Jun 19975 Jun 1997

Conference

ConferenceProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
CityTaipei, China
Period3/06/975/06/97

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