Modeling of the parasitic resistance effect in Poly-Si TFTs with LDD structure

Shih Chin Kao*, Hsiao-Wen Zan, Shih Ching Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this study, the model of poly-Si TFTs with LDD structure had been proposed. Firstly, parasitic resistance parameters were extracted from devices with various channel length and LDD length. Then, an accurate I-V model was constructed by combining basic TFT model (RPI model) and the parasitic resistance effects. The model had been verified for devices with channel length larger than 6 um. The transconductance behavior in both linear region and saturation region are also well explained by our proposed model.

Original languageEnglish
Title of host publicationProceedings of the International Display Manufacturing Conference and Exhibition, IDMC'05
EditorsH.P. David Shieh, F.C. Chen
Pages529-532
Number of pages4
StatePublished - 1 Dec 2005
EventInternational Display Manufacturing Conference and Exhibition, IDMC'05 - Taipei, Japan
Duration: 21 Feb 200524 Feb 2005

Publication series

NameInternational Display Manufacturing Conference and Exhibition, IDMC'05

Conference

ConferenceInternational Display Manufacturing Conference and Exhibition, IDMC'05
CountryJapan
CityTaipei
Period21/02/0524/02/05

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  • Cite this

    Kao, S. C., Zan, H-W., & Chen, S. C. (2005). Modeling of the parasitic resistance effect in Poly-Si TFTs with LDD structure. In H. P. David Shieh, & F. C. Chen (Eds.), Proceedings of the International Display Manufacturing Conference and Exhibition, IDMC'05 (pp. 529-532). (International Display Manufacturing Conference and Exhibition, IDMC'05).