Pocket implant is widely used in deep-sub-micron CMOS technologies to combat short channel effects. It, however, brings anomalously large drain-induced threshold voltage shift and low output resistance to long channel devices. This creates a serious problem for high-performance analog circuits. In this paper, the first physical model of these effects are proposed and verified against data from a 0.18μm technology. This model is suitable for SPICE modeling.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 1999|
|Event||1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA|
Duration: 5 Dec 1999 → 8 Dec 1999