Modeling of direct tunneling current in multi-layer gate stacks

Mohan V. Dunga*, Xuemei Xi, Jin He, Igor Polishchuk, Qiang Lu, Mansun Chan, Ali M. Niknejad, Chen-Ming Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

An analytical direct-tunneling gate current model for multi-layer gate dielectrics is presented. Theoretical derivation shows that the BSIM model for direct tunneling gate current through a single layer also works well for the multi-layer case. The theory is also supported by experimental data. This model is further extended to other modes of tunneling that occur at higher gate voltages. It has been shown that certain stack compositions result in higher leakage current depending on bias conditions. This model also predicts that the effectiveness of high-k dielectrics may decrease due to the reduction of band gap with increase in dielectric constant.

Original languageEnglish
Title of host publication2003 Nanotechnology Conference and Trade Show - Nanotech 2003
EditorsM. Laudon, B. Romanowicz
Pages306-309
Number of pages4
StatePublished - 1 Dec 2003
Event2003 Nanotechnology Conference and Trade Show - Nanotech 2003 - San Francisco, CA, United States
Duration: 23 Feb 200327 Feb 2003

Publication series

Name2003 Nanotechnology Conference and Trade Show - Nanotech 2003
Volume2

Conference

Conference2003 Nanotechnology Conference and Trade Show - Nanotech 2003
CountryUnited States
CitySan Francisco, CA
Period23/02/0327/02/03

Keywords

  • Direct tunneling
  • Gate current
  • Gate stack
  • High-k dielectric

Fingerprint Dive into the research topics of 'Modeling of direct tunneling current in multi-layer gate stacks'. Together they form a unique fingerprint.

Cite this