Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

S. Venugopalan*, Y. S. Chauhan, D. D. Lu, M. A. Karim, Ali M. Niknejad, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaper

2 Scopus citations

Abstract

In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

Original languageEnglish
Pages125-128
Number of pages4
DOIs
StatePublished - 1 Dec 2011
Event2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011 - Shanghai, China
Duration: 7 Nov 20119 Nov 2011

Conference

Conference2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011
CountryChina
CityShanghai
Period7/11/119/11/11

Keywords

  • Asymmetric Transistor Modeling
  • BSIM SPICE Compact Model
  • Vertical Cylindrical/Surround Gate Transistor

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