Modeling geometry-dependent floating-body effect using body-source built-in potential lowering for SOI circuit simulation

Pin Su*, Wei Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a compact silicon-on-insulator (SOI) model to capture the geometry-dependent floating-body effect using the body-source built-in potential lowering approach. This physically accurate model circumvents the modeling challenge imposed by the trend of the coexistence of partial-depletion (PD) and full-depletion (FD) devices in a single SOI chip by considering short-channel, reverse short-channel and reverse narrow-width floating-body effects. The implication on circuit simulation, under the unified Berkeley short-channel IGFET model-silicon-on-insulator (BSIMSOI) framework, has also been addressed. This geometry-dependent body-source built-in potential lowering model will further enhance the device design of scaled SOI complementary metal-oxide-semiconductor (CMOS) below 100 nm.

Original languageEnglish
Pages (from-to)2366-2370
Number of pages5
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume44
Issue number4 B
DOIs
StatePublished - 1 Apr 2005

Keywords

  • Body-source built-in potential lowering
  • Circuit simulation
  • Floating-body effect
  • SOI CMOS

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