Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling

Wen Chin Lee*, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

102 Scopus citations

Abstract

A model is proposed to quantify the tunneling currents through ultra-thin gate oxides. With a proper set of effective mass and barrier height, this new model can accurately predict the gate and substrate currents and all the sub-components in dual-gate CMOS devices. This model can also be employed to extract oxide thickness (Tox) for thin oxide from Ig-Vg data with 0.1 angstroms sensitivity, where CV extraction can be difficult or impossible.

Original languageEnglish
Pages (from-to)198-199
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 1 Jan 2000
Event2000 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 13 Jun 200015 Jun 2000

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