Modeling and formal verification of dataflow graph in system-level design using petri net

Tsung Hsi Chiang, Lan-Rong Dung, Ming Feng Yaung

Research output: Contribution to journalConference article

1 Scopus citations

Abstract

Formal verification in system-level, which also means architecture verification, is different from functional verification in RTL level. DSP algorithms need high-level transformation to achieve optimal goals before mapping on a silicon. However, suitable CAD tool is absent to support the simulation and verification in high-level. This paper presents a novel modeling and high-level verification methodology based on Petri net (PN) model. By proposed method, a system of DSP algorithm in the form of FSFG is transformed into PN model. Moreover, verification methods which include static and dynamical phases are applied in PN domain. At last, we introduce our software implementation, called HiVED, to show the experimental results.

Original languageEnglish
Article number1465925
Pages (from-to)5674-5677
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 1 Dec 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 23 May 200526 May 2005

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