A semiconductor memory with nanocrystal embedded in the gate dielectric was proposed to achieve better retention/programming time ratio. Single-charge tunneling theory with quantum confinement and Coulomb blockade effects was used to model write/erase and retention time of the semiconductor nanocrystal memory devices at room temperature. The impacts of nanocrystal size and tunnel-oxide thickness were also studied. The analysis suggested that flash memory with floating gate structure consumed less power and achieved high array density compared to dynamic random access memory (DRAM).
|Number of pages||2|
|State||Published - 1 Jan 2001|
|Event||Device Research Conference (DRC) - Notre Dame, IN, United States|
Duration: 25 Jun 2001 → 27 Jun 2001
|Conference||Device Research Conference (DRC)|
|City||Notre Dame, IN|
|Period||25/06/01 → 27/06/01|