Modeling and design study of nanocrystal memory devices

M. She*, Y. C. King, T. J. King, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

16 Scopus citations


A semiconductor memory with nanocrystal embedded in the gate dielectric was proposed to achieve better retention/programming time ratio. Single-charge tunneling theory with quantum confinement and Coulomb blockade effects was used to model write/erase and retention time of the semiconductor nanocrystal memory devices at room temperature. The impacts of nanocrystal size and tunnel-oxide thickness were also studied. The analysis suggested that flash memory with floating gate structure consumed less power and achieved high array density compared to dynamic random access memory (DRAM).

Original languageEnglish
Number of pages2
StatePublished - 1 Jan 2001
EventDevice Research Conference (DRC) - Notre Dame, IN, United States
Duration: 25 Jun 200127 Jun 2001


ConferenceDevice Research Conference (DRC)
CountryUnited States
CityNotre Dame, IN

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