This paper reports a model for CMOS inverter propagation delay developed through SPICE simulation and some measurement. Together with the new mobility and the corresponding saturation current device models, projections of future CMOS gate performance within the environment of device scaling and supply voltage shrink are presented.
|Number of pages||4|
|State||Published - 1 Dec 1996|
|Event||Proceedings of the 1996 2nd International Conference on ASIC - Shanghai, China|
Duration: 21 Oct 1996 → 24 Oct 1996
|Conference||Proceedings of the 1996 2nd International Conference on ASIC|
|Period||21/10/96 → 24/10/96|