Model of CMOS gate delay and projection of future trend

Kai Chen*, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper reports a model for CMOS inverter propagation delay developed through SPICE simulation and some measurement. Together with the new mobility and the corresponding saturation current device models, projections of future CMOS gate performance within the environment of device scaling and supply voltage shrink are presented.

Original languageEnglish
Pages436-439
Number of pages4
DOIs
StatePublished - 1 Dec 1996
EventProceedings of the 1996 2nd International Conference on ASIC - Shanghai, China
Duration: 21 Oct 199624 Oct 1996

Conference

ConferenceProceedings of the 1996 2nd International Conference on ASIC
CityShanghai, China
Period21/10/9624/10/96

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