This paper describes how rapid model-year architectural synthesis (e.g., HW/SW codesign) of embedded signal processors can be performed to optimize various cost objective functions using a reuse library of models, followed by simulation based optimization. Sponsored as part of DARPA's RASSP program, this approach has developed and released a number of interoperable and verified architectural component libraries at the system level (processors, communication protocols, and topologies). While these libraries have been used in actual demonstrations of avionics and military systems, such as the MIT Lincoln Laboratory's SAR Benchmark, the F-14 legacy Infrared Search and Track System (IRST), and as part of NASA/JPL's Remote Exploration/Experimentation (REE) program studies, we introduce the methodology of conceptual prototyping and establish the requirements and features of the proposed environment. We also illustrate its use on some common applications with relatively sophisticated architectural building blocks, such as IEEE SCI protocol and Analog Devices' SHARC processor family.
|Number of pages||10|
|State||Published - 1 Dec 1996|
|Event||Proceedings of the 1996 9th IEEE Workshop on VLSI Signal Processing - San Francisco, CA, USA|
Duration: 30 Oct 1996 → 1 Nov 1996
|Conference||Proceedings of the 1996 9th IEEE Workshop on VLSI Signal Processing|
|City||San Francisco, CA, USA|
|Period||30/10/96 → 1/11/96|