Model-based architectural design and verification of scalable embedded DSP systems - a RASSP approach

Lan-Rong Dung*, V. K. Madisetti, J. W. Hines

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper describes how rapid model-year architectural synthesis (e.g., HW/SW codesign) of embedded signal processors can be performed to optimize various cost objective functions using a reuse library of models, followed by simulation based optimization. Sponsored as part of DARPA's RASSP program, this approach has developed and released a number of interoperable and verified architectural component libraries at the system level (processors, communication protocols, and topologies). While these libraries have been used in actual demonstrations of avionics and military systems, such as the MIT Lincoln Laboratory's SAR Benchmark, the F-14 legacy Infrared Search and Track System (IRST), and as part of NASA/JPL's Remote Exploration/Experimentation (REE) program studies, we introduce the methodology of conceptual prototyping and establish the requirements and features of the proposed environment. We also illustrate its use on some common applications with relatively sophisticated architectural building blocks, such as IEEE SCI protocol and Analog Devices' SHARC processor family.

Original languageEnglish
Pages147-156
Number of pages10
DOIs
StatePublished - 1 Dec 1996
EventProceedings of the 1996 9th IEEE Workshop on VLSI Signal Processing - San Francisco, CA, USA
Duration: 30 Oct 19961 Nov 1996

Conference

ConferenceProceedings of the 1996 9th IEEE Workshop on VLSI Signal Processing
CitySan Francisco, CA, USA
Period30/10/961/11/96

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