Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3×VDD input tolerance by using 1×VDD devices and single VDD supply

Ming-Dou Ker*, Shih Lun Chen

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

20 Scopus citations

Abstract

This work presents a mixed-voltage I/O buffer realized with 1×V DD devices and single VDD power supply to receive 3×VDD input signals without suffering gate-oxide reliability problems. The proposed I/O buffer is verified in a 0.13μm 1V CMOS process. This technique can be extended to receive 4×VDD, 5×V DD, and even 6×VDD input signals.

Original languageEnglish
Article number28.8
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume48
DOIs
StatePublished - 6 Dec 2005
Event2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 6 Feb 200510 Feb 2005

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