This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm2 core by 0.8 μm SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong|
Duration: 9 Jun 1997 → 12 Jun 1997