Phased-array signal processor sections have been implemented in a mixed analog/digital VLSI circuit. The monolithic circuit is used to digitize two channels of analog signals, compress or decompress the data, and impose the necessary time delays for coherent summation. 50 ns time delay quantization per channel was achieved by rephasing the A/D triggers at appropriate times in the beam formation, and properly adjusting the lengths of the fine time delays. The chip has also been tested in a system environment at the 10-MHz system clock rate and is the key component of the digital front end of a phased-array system.
|Pages (from-to)||58-59, 298|
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|State||Published - 1 Dec 1988|