Minimized transient and steady-state cross regulation in 55nm CMOS single-inductor dual-output (SIDO) step-down DC-DC converter

Yu Huei Lee; Tzu Chi Huang; Yao Yi Yang; Ke-Horng Chen; Ying Hsi Lin; Wen Shen Chou; Chen Chih Huang; Yi Kuang Chen

doi:10.1109/ASSCC.2010.5716558

Minimized transient and steady-state cross regulation in 55nm CMOS single-inductor dual-output (SIDO) step-down DC-DC converter

Yu Huei Lee^*, Tzu Chi Huang, Yao Yi Yang, Ke-Horng Chen, Ying Hsi Lin, Wen Shen Chou, Chen Chih Huang, Yi Kuang Chen

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A single-inductor dual-output (SIDO) step-down converter with continuous conduction mode (CCM) control is proposed for high efficiency system-on-a-chip (Soc) integration. The cross regulation in steady-state output voltage ripple, which is rarely mentioned, is effectively reduced as well as in transient response. The low-voltage energy distribution controller (LV-EDC) circuit guarantees good voltage regulation and low output voltage ripple simultaneously. In addition, within the allowable output voltage ripple, the automatic energy bypass (AEB) mechanism can reduce the number of energy delivery path to decrease the switching loss. Two outputs are operated with the load-dependent energy path for improving the power conversion efficiency. The chip fabricated in 55 nm CMOS achieves 91 % peak efficiency, low output voltage ripple, and excellent load transient response.

Original language	English
Title of host publication	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages	65-68
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2010.5716558
State	Published - 1 Dec 2010
Event	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China Duration: 8 Nov 2010 → 10 Nov 2010

Publication series

Name	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Conference

Conference	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Country	China
City	Beijing
Period	8/11/10 → 10/11/10

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Lee, Y. H., Huang, T. C., Yang, Y. Y., Chen, K-H., Lin, Y. H., Chou, W. S., Huang, C. C., & Chen, Y. K. (2010). Minimized transient and steady-state cross regulation in 55nm CMOS single-inductor dual-output (SIDO) step-down DC-DC converter. In 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 (pp. 65-68). [5716558] (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010). https://doi.org/10.1109/ASSCC.2010.5716558

Lee, Yu Huei ; Huang, Tzu Chi ; Yang, Yao Yi ; Chen, Ke-Horng ; Lin, Ying Hsi ; Chou, Wen Shen ; Huang, Chen Chih ; Chen, Yi Kuang. / Minimized transient and steady-state cross regulation in 55nm CMOS single-inductor dual-output (SIDO) step-down DC-DC converter. 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. pp. 65-68 (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010).

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title = "Minimized transient and steady-state cross regulation in 55nm CMOS single-inductor dual-output (SIDO) step-down DC-DC converter",

abstract = "A single-inductor dual-output (SIDO) step-down converter with continuous conduction mode (CCM) control is proposed for high efficiency system-on-a-chip (Soc) integration. The cross regulation in steady-state output voltage ripple, which is rarely mentioned, is effectively reduced as well as in transient response. The low-voltage energy distribution controller (LV-EDC) circuit guarantees good voltage regulation and low output voltage ripple simultaneously. In addition, within the allowable output voltage ripple, the automatic energy bypass (AEB) mechanism can reduce the number of energy delivery path to decrease the switching loss. Two outputs are operated with the load-dependent energy path for improving the power conversion efficiency. The chip fabricated in 55 nm CMOS achieves 91 % peak efficiency, low output voltage ripple, and excellent load transient response.",

author = "Lee, {Yu Huei} and Huang, {Tzu Chi} and Yang, {Yao Yi} and Ke-Horng Chen and Lin, {Ying Hsi} and Chou, {Wen Shen} and Huang, {Chen Chih} and Chen, {Yi Kuang}",

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doi = "10.1109/ASSCC.2010.5716558",

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Lee, YH, Huang, TC, Yang, YY, Chen, K-H, Lin, YH, Chou, WS, Huang, CC & Chen, YK 2010, Minimized transient and steady-state cross regulation in 55nm CMOS single-inductor dual-output (SIDO) step-down DC-DC converter. in 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010., 5716558, 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, pp. 65-68, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, Beijing, China, 8/11/10. https://doi.org/10.1109/ASSCC.2010.5716558

Minimized transient and steady-state cross regulation in 55nm CMOS single-inductor dual-output (SIDO) step-down DC-DC converter. / Lee, Yu Huei; Huang, Tzu Chi; Yang, Yao Yi; Chen, Ke-Horng; Lin, Ying Hsi; Chou, Wen Shen; Huang, Chen Chih; Chen, Yi Kuang.

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. p. 65-68 5716558 (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lee, Yu Huei

AU - Huang, Tzu Chi

AU - Yang, Yao Yi

AU - Chen, Ke-Horng

AU - Lin, Ying Hsi

AU - Chou, Wen Shen

AU - Huang, Chen Chih

AU - Chen, Yi Kuang

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AB - A single-inductor dual-output (SIDO) step-down converter with continuous conduction mode (CCM) control is proposed for high efficiency system-on-a-chip (Soc) integration. The cross regulation in steady-state output voltage ripple, which is rarely mentioned, is effectively reduced as well as in transient response. The low-voltage energy distribution controller (LV-EDC) circuit guarantees good voltage regulation and low output voltage ripple simultaneously. In addition, within the allowable output voltage ripple, the automatic energy bypass (AEB) mechanism can reduce the number of energy delivery path to decrease the switching loss. Two outputs are operated with the load-dependent energy path for improving the power conversion efficiency. The chip fabricated in 55 nm CMOS achieves 91 % peak efficiency, low output voltage ripple, and excellent load transient response.

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Lee YH, Huang TC, Yang YY, Chen K-H, Lin YH, Chou WS et al. Minimized transient and steady-state cross regulation in 55nm CMOS single-inductor dual-output (SIDO) step-down DC-DC converter. In 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. p. 65-68. 5716558. (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010). https://doi.org/10.1109/ASSCC.2010.5716558