TY - JOUR
T1 - Minimized transient and steady-state cross regulation in 55-nm CMOS single-inductor dual-output (SIDO) step-down DC-DC converter
AU - Lee, Yu Huei
AU - Huang, Tzu Chi
AU - Yang, Yao Yi
AU - Chou, Wen Shen
AU - Chen, Ke-Horng
AU - Huang, Chen Chih
AU - Lin, Ying Hsi
PY - 2011/11/1
Y1 - 2011/11/1
N2 - A single-inductor dual-output (SIDO) step-down DC-DC converter with continuous conduction mode (CCM) operation is proposed to achieve an area-efficient power management module. The low-voltage energy distribution controller (LV-EDC) can simultaneously guarantee good voltage regulation and low output voltage ripple. With the proposed dual-mode energy delivery methodology, cross regulation in steady-state output voltage ripple, which is rarely discussed, and cross regulation in load transient response are both effectively reduced. In addition, the energy mode transition operation helps obtain the appropriate energy operation mode using the energy delivery paths for dual outputs. Moreover, within the allowable output voltage ripple, the automatic energy bypass (AEB) mechanism can reduce the number of energy delivery paths, thereby ensuring voltage regulation and further enhancing efficiency. The test chip, fabricated in 55-nm CMOS, occupies 1.44 mm2 and achieves 91% peak efficiency, low output voltage ripple, and excellent load transient response for a high-efficiency system-on-a-chip (SoC) integration.
AB - A single-inductor dual-output (SIDO) step-down DC-DC converter with continuous conduction mode (CCM) operation is proposed to achieve an area-efficient power management module. The low-voltage energy distribution controller (LV-EDC) can simultaneously guarantee good voltage regulation and low output voltage ripple. With the proposed dual-mode energy delivery methodology, cross regulation in steady-state output voltage ripple, which is rarely discussed, and cross regulation in load transient response are both effectively reduced. In addition, the energy mode transition operation helps obtain the appropriate energy operation mode using the energy delivery paths for dual outputs. Moreover, within the allowable output voltage ripple, the automatic energy bypass (AEB) mechanism can reduce the number of energy delivery paths, thereby ensuring voltage regulation and further enhancing efficiency. The test chip, fabricated in 55-nm CMOS, occupies 1.44 mm2 and achieves 91% peak efficiency, low output voltage ripple, and excellent load transient response for a high-efficiency system-on-a-chip (SoC) integration.
KW - Cross regulation
KW - energy bypass mechanism
KW - energy delivery path
KW - load transient response
KW - output voltage ripple
KW - power conversion efficiency
KW - single-inductor dual-output (SIDO) converter
UR - http://www.scopus.com/inward/record.url?scp=80255129197&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2011.2164019
DO - 10.1109/JSSC.2011.2164019
M3 - Article
AN - SCOPUS:80255129197
VL - 46
SP - 2488
EP - 2499
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 11
M1 - 6016217
ER -