Miniaturized 3-dimensional transformer design

Wei-Zen Chen*, Kuo Ching Hsu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

3-dimentional fully-symmetric transformers are proposed and realized in a standard CMOS technology. In contrast to their planar counterparts, the self resonant frequency (fSR) of the proposed architecture is improved by 26 % to 53 %, while the chip area is reduced by 40 % to 70 %. The coupling coefficient (K) can be up to 0.77 at 8 GHz in a two turn two layer architecture. Distributed capacitance model (DCM) of the 3-D transformer is also proposed for fSR evaulation.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2005 Custom Integrated Circuits Conference
Pages278-281
Number of pages4
DOIs
StatePublished - 1 Dec 2005
EventIEEE 2005 Custom Integrated Circuits Conference - San Jose, CA, United States
Duration: 18 Sep 200521 Sep 2005

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2005
ISSN (Print)0886-5930

Conference

ConferenceIEEE 2005 Custom Integrated Circuits Conference
CountryUnited States
CitySan Jose, CA
Period18/09/0521/09/05

Keywords

  • Coupling coefficient
  • Self resonant frequency
  • Transformer

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    Chen, W-Z., & Hsu, K. C. (2005). Miniaturized 3-dimensional transformer design. In Proceedings of the IEEE 2005 Custom Integrated Circuits Conference (pp. 278-281). [1568661] (Proceedings of the Custom Integrated Circuits Conference; Vol. 2005). https://doi.org/10.1109/CICC.2005.1568661