Microanalysis of VLSI interconnect failure modes under short-pulse stress conditions

Kaustav Banerjee*, Dae Yong Kim, Ajith Amerasekera, Chen-Ming Hu, S. Simon Wong, Kenneth E. Goodson

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

21 Scopus citations


This work presents a detailed microanalysis of interconnect failure mechanisms under short-pulse stress conditions arising during peak current and electrostatic discharge (ESD) events. TEM and SEM analysis have been used to show that passivated AlCu lines can undergo localized melting and voiding under sub-critical current pulses that heat the lines well past their melting point but below a critical failure temperature causing open circuit failures. It is observed that the damage caused by the melting and voiding remains latent since no physical evidence of damage can be detected under optical microscope and no change in the electrical resistance of these lines can be measured. The voids observed under TEM and SEM result from electromigration under very high current densities and high temperature. TEM diffraction patterns confirm that the molten regions exhibit smaller grain sizes, which are introduced as a result of rapid resolidification from a molten state. A thermo-mechanical model has also been formulated to account for the open circuit failure mode at which the passivation layers are fractured.

Original languageEnglish
Pages (from-to)283-288
Number of pages6
JournalAnnual Proceedings - Reliability Physics (Symposium)
StatePublished - 1 Jan 2000
Event38th IEEE International Reliability Physics Symposium - San Jose, CA, USA
Duration: 10 Apr 200013 Apr 2000

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