Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology

Hsin Chyh Hsu*, Chi Ming Chen, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

NMOS with dummy-gate structure is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, the ESD current is discharged far away from the salicided surface channel of NMOS, therefore NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress.

Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers
Pages19-20
Number of pages2
DOIs
StatePublished - 31 Oct 2005
Event2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH - Hsinchu, Taiwan
Duration: 25 Apr 200527 Apr 2005

Publication series

Name2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

Conference

Conference2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH
CountryTaiwan
CityHsinchu
Period25/04/0527/04/05

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