Methods for power/throughput/area optimization of H.264/AVC decoding

Ke Xu*, Tsu Ming Liu, Jiun-In Guo, Chiu Sing Choy

*Corresponding author for this work

Research output: Contribution to journalArticle

7 Scopus citations


This paper presents methods for efficient optimization of ASIC implementation for H.264/AVC video decoding. A systematic approach in optimization is presented in a top-down flow. Tradeoffs among Power, Throughput, and Area (PTA) at both system level and block level are studied and balanced. The system architecture is first evaluated. We then focus on the pipeline organization, parallelism, and memory architecture optimization. Different pipeline granularities are compared and their pros-and-cons are evaluated. Various parallel scenarios, especially 1×4-column and 4×1-row, are analyzed and compared. Then the detailed designs of various building blocks, such as inverse transform, inter prediction, and deblocking filter, are evaluated and their intrinsic characteristics are exploited to facilitate PTA optimization. Finally, we provide the design guidelines for ASIC implementation based on the analysis and our design experiences of five dedicated decoder chips.

Original languageEnglish
Pages (from-to)131-145
Number of pages15
JournalJournal of Signal Processing Systems
Issue number1
StatePublished - 1 Jul 2010


  • ASIC
  • Cost
  • Decoding
  • H.264/AVC
  • Memory
  • Performance
  • Power

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