Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology

Ming-Dou Ker*, Wen Yu Lo

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

44 Scopus citations

Abstract

An experimental methodology to find area-efficient compact layout rules to prevent latchup in bulk complimentary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new latchup prevention design by adding the additional internal double guard rings between input/output cells and internal circuits is first reported in the literature, and its effectiveness has been successfully proven in three different bulk CMOS processes. Through detailed experimental verification including temperature effect, the proposed methodology to extract compact layout rules has been established to save silicon area of CMOS ICs but still to have high enough latchup immunity. This proposed methodology has been successfully verified in a 0.5-μm nonsilicided, a 0.35-μm suicided, and a 0.25-μm suicided shallow-trench-isolation bulk CMOS processes.

Original languageEnglish
Pages (from-to)319-334
Number of pages16
JournalIEEE Transactions on Semiconductor Manufacturing
Volume16
Issue number2
DOIs
StatePublished - 1 May 2003

Keywords

  • Design rule
  • Guard ring
  • I/O cell
  • Latchup
  • Pickup

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