Methodology of generating dual-cell-aware tests

Yu Hao Huang, Ching Ho Lu, Tse Wei Wu, Yu Teng Nien, Ying Yen Chen, Max Wu, Jih Nung Lee, Chia-Tso Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper introduces a novel fault model, called the dual-cell-Aware (DCA) fault model, which targets the short defects locating between two adjacent standard cells placed in the layout. A layout-based methodology is also presented to automatically extract valid DCA faults from targeted designs and cell libraries. The identified DCA faults are outputted in a format that can be applied to a commercial ATPG tool for test generation. The result of ATPG and fault simulation based on industrial designs have demonstrated that the DCA faults cannot be fully covered by the tests of conventional fault models including stuck-At, transition, bridge and cell-Aware faults and hence require their own designated tests to detect.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE 35th VLSI Test Symposium, VTS 2017
PublisherIEEE Computer Society
ISBN (Electronic)9781509044825
DOIs
StatePublished - 15 May 2017
Event35th IEEE VLSI Test Symposium, VTS 2017 - Las Vegas, United States
Duration: 9 Apr 201712 Apr 2017

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference35th IEEE VLSI Test Symposium, VTS 2017
CountryUnited States
CityLas Vegas
Period9/04/1712/04/17

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  • Cite this

    Huang, Y. H., Lu, C. H., Wu, T. W., Nien, Y. T., Chen, Y. Y., Wu, M., Lee, J. N., & Chao, C-T. (2017). Methodology of generating dual-cell-aware tests. In Proceedings - 2017 IEEE 35th VLSI Test Symposium, VTS 2017 [7928925] (Proceedings of the IEEE VLSI Test Symposium). IEEE Computer Society. https://doi.org/10.1109/VTS.2017.7928925