Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation

Nan Chun Lien, Ching Te Chuang, Wen-Rong Wu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This work proposes a novel Dual-Port (DP) 8T SRAM operation scheme. The scheme improves the Read stability and Write-ability, and allows asynchronous operation with arbitrary clock timing skew between two ports. It facilitates high performance, low-power and low VMIN with minimum device and area overhead. Post-simulation results show almost no timing penalty for simultaneous same-row access and the performance is almost the same as that for one port operation.

Original languageEnglish
Title of host publicationProceedings - IEEE 26th International SOC Conference, SOCC 2013
PublisherIEEE Computer Society
Pages105-109
Number of pages5
ISBN (Print)9781479911660
DOIs
StatePublished - 1 Jan 2013
Event26th IEEE International System-on-Chip Conference, SOCC 2013 - Erlangen, Germany
Duration: 4 Sep 20136 Sep 2013

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference26th IEEE International System-on-Chip Conference, SOCC 2013
CountryGermany
CityErlangen
Period4/09/136/09/13

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