Metal nanocrystal/nitride heterogeneous-stack floating gate memory

Chungho Lee*, Tuo-Hung Hou, Edwin C. Kan

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations


Nonvolatile memories with heterogeneous-stack floating gate of metal nanocrystals and silicon nitride (Si3N4) have been fabricated and characterized. The heterogeneous gate stacks showed superior characteristics in retention and low voltage write/erase over single metal nanocrystal memories and/or nitride memories (i.e., MONOS or SONOS). The metal nanocrystals in the stack made low voltage operation possible by the direct tunneling programming, while the nitride layer as an additional charge storage trap layer enabled longer retention time. By making the double stack of Si 3N4-Au- Si3N4-Au, we could enhance the memory characteristics even further. Local charge storage in the floating gate of Flash memory devices enables the aggressive scaling of the tunneling oxide by relieving the total charge loss concern of the continuous floating gate [1]. Possible direct adaptation to the current nonvolatile memory technology is also one of its merits. However, there remains a trade-off between the retention and write/erase characteristics in charge-based memory operations. Nanocrystal memories with oxide in the direct tunneling regime suffer the retention degradation. SONOS, on the other hand, needs high operational voltage. In this study, the heterogeneous stack with metal nanocrystals and nitride is investigated as a promising combination. Semiconductor nanocrystal (Si) and SONOS hybrid memories have been proposed [2, 3]. However, the metal nanocrystals can be more advantageous as the intermediate media and offer larger charge storage capacity and longer retention time than semiconductor counterparts [4]. The device schematics of single and double heterogeneous stack floating gate structures are shown in Fig. 1. Au nanocrystals were self-assembled after 1.2nm thick metal evaporation on top of 2.65nm tunneling oxide. Then 8.6nm PECVD nitride and 29.9nm PECVD oxide depositions were performed. For double stack in Fig. 1 (b), each nanocrystal formation was followed by 4.3nm nitride deposition. The discrete Au nanocrystal formation was confirmed by SEM observation before capping with other materials in Fig. 2. To characterize the metal nanocrystal/nitride gate stack, the cross-sectional STEM image of double heterogeneous stack was prepared, which are embedded in the SiO2 in Fig. 3. As describe in Table 1, 5 floating gate splits were prepared: (a) control, (b) nitride, (c) Au nanocrystal, (d) single heterogeneous, and (e) double stacks. For fair comparison, all other fabrication conditions are set to be the same, and batch processing of growth and etch is performed whenever feasible. Electrical characterization by 1MHz C-V measurements demonstrates the advantage of heterogeneous stack memories. Devices with Au nanocrystals in Figs. 4 (c), (d), and (e) show the memory windows of 0.89V, 1.12V, and 3V, respectively. The detailed summary of write/erase test is shown in Fig. 5. The rates of the flat band voltage shift over the gate voltage (ΔV FB/VG) are 0.5(c) < 0.84(d) < 0.96(e) for erasing, and 0.21(c) < 0.34(d) < 0.56(e) for writing. It proves that Au nanocrystals work as an ideal medium to the nitride traps, and that double stack is more efficient than single stack. It can be conjectured that the additional nanocrystal layer can help the charge transfer to the farther traps from the channel. The quality of gate oxide is verified from minimum hysteresis in the control sample of Fig. 4 (a). For nitride (SONOS), the extended write/erase test was carried out up to ±20V in Fig. 6. It requires the high write/erase voltages over ±10V to give a detectable flat band voltage shift. Retention characteristics manifest the key role of nitride traps. At room temperature, reasonable retention in a give time span for all three splits was obtained, but the high temperature tests in Fig. 8 distinguish the characteristics by accelerating the charge loss. Because the elevated temperature of 80°C can agitate the stored charge in the nanocrystals, the fast collapse of capacitance is observed in nanocrystal sample (c). However, the heterogeneous stack with nitride seems to make the relaxation to the traps and maintain the stored charges for long retention. Endurance test in Fig. 9 was performed up to 106 cycles. Because direct tunneling mechanism ensures the minimal oxide degradation, all devices do not show any significant memory window variation, but a small fluctuation from capacitance measurements. The write/erase tests in Figs. 10 and 11 show 0.5-15V flat band voltage shift in less than 100ns, and the charge saturation in less than 10μsec for devices (c) and (d). However, owing to the large charge storage capacity, the charge saturation time of device (e) is around 100μsec with a large 3V flat band voltage shift. We demonstrated that the heterogeneous-stack floating gate of metal nanocrystals and nitride has significant advantages in the retention characteristics and low voltage operations. From the comparison of five gate stack splits, the roles of nitride traps for longer retention and nanocrystals for low voltage write/erase are demonstrated.

Original languageEnglish
Title of host publication63rd Device Research Conference Digest, DRC'05
Number of pages2
StatePublished - 1 Dec 2005
Event63rd Device Research Conference, DRC'05 - Santa Clara, CA, United States
Duration: 20 Jun 200522 Jun 2005

Publication series

NameDevice Research Conference - Conference Digest, DRC
ISSN (Print)1548-3770


Conference63rd Device Research Conference, DRC'05
CountryUnited States
CitySanta Clara, CA

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