Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT

Albert Chin*, W. B. Chen, B. S. Shie, K. C. Hsu, P. C. Chen, C. H. Cheng, C. C. Chi, Y. H. Wu, K. S. Chaing-Liaoc, S. J. Wang, C. H. Kuan, F. S. Yeh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6∼1 nm EOT and low Vt of ∼0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET that has 2.5X better high-field hole effective mobility than the SiO2/Si universal mobility at an E eff of 1 MV/cm.

Original languageEnglish
Title of host publicationICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages836-839
Number of pages4
DOIs
StatePublished - 1 Dec 2010
Event2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
Duration: 1 Nov 20104 Nov 2010

Publication series

NameICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

Conference2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
CountryChina
CityShanghai
Period1/11/104/11/10

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