Memory-based architecture for very-high-throughput variable length codec design

Yew San Lee; Jin Jer Jong; Tsyr Shiou Perng; Li Chyun Hsu; Ming Yang Jaw; Chen-Yi Lee

doi:10.1109/ISCAS.1997.621570

Memory-based architecture for very-high-throughput variable length codec design

Yew San Lee^*, Jin Jer Jong, Tsyr Shiou Perng, Li Chyun Hsu, Ming Yang Jaw, Chen-Yi Lee

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

Variable-length code/decode (VLC/NLD) is the most popular data compression technique which can reduce the storage and communication channel bandwidth needed to transmit a large amount of data. In this paper, we present a new memory-based VLSI architecture for VLC/VLD codec system. Both coding and decoding procedures are mapped onto a memory which has been minimized by using a two-bit structure. The proposed architecture mainly consists of memory and simple arithmetic unit, making it very suitable for VLSI implementation. Simulation results show that based on 0.35 um CMOS process, both compression rate and decompression rate up to 1.2 Gbits/s can be achieved.

Original language	English
Pages (from-to)	2096-2099
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
DOIs	https://doi.org/10.1109/ISCAS.1997.621570
State	Published - 1 Jan 1997
Event	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong Duration: 9 Jun 1997 → 12 Jun 1997

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title = "Memory-based architecture for very-high-throughput variable length codec design",

abstract = "Variable-length code/decode (VLC/NLD) is the most popular data compression technique which can reduce the storage and communication channel bandwidth needed to transmit a large amount of data. In this paper, we present a new memory-based VLSI architecture for VLC/VLD codec system. Both coding and decoding procedures are mapped onto a memory which has been minimized by using a two-bit structure. The proposed architecture mainly consists of memory and simple arithmetic unit, making it very suitable for VLSI implementation. Simulation results show that based on 0.35 um CMOS process, both compression rate and decompression rate up to 1.2 Gbits/s can be achieved.",

author = "Lee, {Yew San} and Jong, {Jin Jer} and Perng, {Tsyr Shiou} and Hsu, {Li Chyun} and Jaw, {Ming Yang} and Chen-Yi Lee",

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AU - Lee, Yew San

AU - Jong, Jin Jer

AU - Perng, Tsyr Shiou

AU - Hsu, Li Chyun

AU - Jaw, Ming Yang

AU - Lee, Chen-Yi

PY - 1997/1/1

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N2 - Variable-length code/decode (VLC/NLD) is the most popular data compression technique which can reduce the storage and communication channel bandwidth needed to transmit a large amount of data. In this paper, we present a new memory-based VLSI architecture for VLC/VLD codec system. Both coding and decoding procedures are mapped onto a memory which has been minimized by using a two-bit structure. The proposed architecture mainly consists of memory and simple arithmetic unit, making it very suitable for VLSI implementation. Simulation results show that based on 0.35 um CMOS process, both compression rate and decompression rate up to 1.2 Gbits/s can be achieved.

AB - Variable-length code/decode (VLC/NLD) is the most popular data compression technique which can reduce the storage and communication channel bandwidth needed to transmit a large amount of data. In this paper, we present a new memory-based VLSI architecture for VLC/VLD codec system. Both coding and decoding procedures are mapped onto a memory which has been minimized by using a two-bit structure. The proposed architecture mainly consists of memory and simple arithmetic unit, making it very suitable for VLSI implementation. Simulation results show that based on 0.35 um CMOS process, both compression rate and decompression rate up to 1.2 Gbits/s can be achieved.

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M3 - Conference article

AN - SCOPUS:0030685337

VL - 3

SP - 2096

EP - 2099

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

Y2 - 9 June 1997 through 12 June 1997

ER -

Memory-based architecture for very-high-throughput variable length codec design

Abstract

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