Memory-based architecture for very-high-throughput variable length codec design

Yew San Lee*, Jin Jer Jong, Tsyr Shiou Perng, Li Chyun Hsu, Ming Yang Jaw, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

5 Scopus citations

Abstract

Variable-length code/decode (VLC/NLD) is the most popular data compression technique which can reduce the storage and communication channel bandwidth needed to transmit a large amount of data. In this paper, we present a new memory-based VLSI architecture for VLC/VLD codec system. Both coding and decoding procedures are mapped onto a memory which has been minimized by using a two-bit structure. The proposed architecture mainly consists of memory and simple arithmetic unit, making it very suitable for VLSI implementation. Simulation results show that based on 0.35 um CMOS process, both compression rate and decompression rate up to 1.2 Gbits/s can be achieved.

Original languageEnglish
Pages (from-to)2096-2099
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
DOIs
StatePublished - 1 Jan 1997
EventProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong
Duration: 9 Jun 199712 Jun 1997

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