Memory-based approach to the design of efficient VLSI arrays for the multi-dimensional discrete Hartley transform

The design of the multi-dimensional (M-D) discrete Hartley transform (DTH) involves two fundamental difficulties: the inseparability of the M-D DHT and the implementation of function units in very large scale integration (VLSI) architectures. The inseparability of M-D DHT yields much overhead in VLSI implementation, and the implementation of function units directly influences the performance of the designed architectures. To conquer these difficulties, in this paper, we present a memory-based approach which can be used to design efficient VLSI arrays for the M-D DHT. This approach derives a new formulation for the M-D DHT such that we can eliminate the undesirable overhead needed in former designs. Moreover, the presented approach can formulate the M-D DHT with any length as a cyclic convolution, realize it by means of a systolic array, and implement it using small read only memory (ROM) and adders, which are designated as memory-based implementation. Using cyclic convolution provides the advantages of high computing parallelism and low computation complexity. Using systolic array realization results in high computing speeds, low input/output (I/O) cost, and high feasibility for VLSI implementation. Adopting the memory-based implementation greatly reduces the hardware cost. This implementation scheme is more hardware-efficient than the well-known distributed arithmetic (DA) technique. To sum up, the presented memory-based design approach will lead to efficient VLSI implementation of M-D DHT.