Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

Jen Chou Tseng*, Yu Lin Chen, Chung Ti Hsu, Fu Yi Tsai, Po An Chen, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated circuits. The latchup test resulted in damage to the output NMOSFET due to snapback and also resulted in a latchup in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.

Original languageEnglish
Title of host publication46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS
Pages625-626
Number of pages2
DOIs
StatePublished - 17 Sep 2008
Event46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS - Phoenix, AZ, United States
Duration: 27 Apr 20081 May 2008

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Conference

Conference46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS
CountryUnited States
CityPhoenix, AZ
Period27/04/081/05/08

Keywords

  • EOS
  • ESD
  • High-voltage
  • Latch-up

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    Tseng, J. C., Chen, Y. L., Hsu, C. T., Tsai, F. Y., Chen, P. A., & Ker, M-D. (2008). Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits. In 46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS (pp. 625-626). [4558958] (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/RELPHY.2008.4558958