Although high channel electron mobility has been reported after some passivation techniques, the performance of n-channel Ge metal-oxide- semiconductor field-effect transistor is still limited by the high Schottky barrier height at the metal/n-Ge contact interface, which comes from the Fermi level pinning effect. Recent experiments demonstrated that the Schottky barrier height can be reduced by inserting a thin dielectric layer between metal and Ge. However, the mechanism has not been well clarified. In this paper, the metal induced gap state model, the dipole layer model, and the fixed charge model are verified by varying contact metals, dielectric thicknesses, as well as the annealing temperatures. The pinning factor is improved slightly by dielectric insertion but its value is independent of the dielectric thickness and is still much lower than the ideal value of the non-pinning case. This pinning effect is consistent with the Fermi level pinning at the metal/TiO2 interface. After thermal process, no interfacial layer forms at the TiO2/Ge interface and the TiO2 crystallizes gradually after annealing but the Schottky barrier height increases. Since the amount of fixed charges in the thin dielectric layer estimated from a metal-insulator-semiconductor structure is about 2 × 1011 cm-2 and is insufficient to produce the observed 0.5 eV Schottky barrier height reduction, it is thus recommended that the main mechanism comes from the change of interface dipoles and the annealing effect is attributed to the short-range ordering of the TiO2 layer. Furthermore, dielectric with low conduction band offset which has good thermal stability should be explored.