Silicon-on-insulator (SOI) technology has been considered capable of developing devices with high tolerance against soft error. With a thin buried oxide (BOX) layer, reduction in power consumption can be achieved by applying a back bias from under the BOX. Such power reduction is one of its many advantages and is appealing to space applications. Recently, it was found during a heavy ion experiment that a static random access memory (SRAM) fabricated with a thin-BOX SOI technology exhibits a 100-fold soft error sensitivity when it receives a back-bias. This is due to long line-type formation of multiple cell upsets (MCUs). To understand the mechanism of this phenomenon and the effects of device parameters on it, an analytical model is developed and studied with numerical simulation. On the basis of the model, a countermeasure is also discussed. It is found that the deep n-well doping concentration or resistance plays an important role in the phenomenon and its countermeasure.