Recently, CMOS downsizing has been accelerated very aggressively in both production and research levels, and even beautiful transistor operation of several nm gate length CMOS devices were reported in conferences. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits. It is still questionable if we can successfully introduce deep sub-10 nm CMOS LSIs into market, because the problems expected at this moment - such as I on/I off ratio, current drive, variation in the electrical characteristics, concerns for the yield, reliability and manufacturing cost. Considering the above situation, we have conducted nano-CMOS studies in advance to provide possible solutions to the future expected problems. The conclusion obtained by the study was that, in the nano-CMOS era, aggressive introduction of new materials, processes, structures, and operation concepts is required to solve the problems. Especially, the thinning of the gate oxide is the bottleneck of the future down-scaling, and thus, new materials and process technologies which enable decrease in the EOT (Equivalent Oxide Thickness) value less than 0.5 nm are very important. Also, changing the material of source/drain from semiconductor to metal is necessary to suppression of the diffusion of the dopant and thus, to secure the effective channel length less than several nm. Multigate structure such as Fin, Tri-gate, or nanowire is inevitable to suppress the short-channel effect. Unfortunately, there are no candidates among the so-called 'beyond CMOS' or 'Post Si' new devices, which are believed to really replace CMOS transistors usable for the products of highly integrated circuits within 20 years. Thus, our opinion is that we need to still continue CMOS based transistors with 'More Moore' approach with combining that of 'More than Moore'. Good news is that Si Nanowire FETs have been found to have very promising characteristics with high I on/I off ratio and high drive current. In this invited talk at NMDC 2011, future of nano-CMOS technology is presented. However, in this proceedings, only the part of new structure for future nano-CMOS, specifically that of Si-nanowire FETs is described because the limit of the number of pages.