MapReduce-based pattern classification for design space analysis

Yan Shiun Wu, Hong Yan Su, Yi Hsiang Chang, Rasit Onur Topaloglu, Yih-Lang Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

With the ongoing reduction of feature size, design for manufacturability is a critical concern in advanced technology nodes. Pattern classification is a promising and widely employed approach for design space analysis, design rule generation, and yield optimization. In this paper, we propose a hybrid algorithm that account for two variations for classification metrics: feature edge displacement and total feature area difference. A MapRe-duce-based framework is proposed to reduce the complexity of the pattern classification problem such that orders of magnitude of performance improvement can be realized. Our experimental results indicate that regarding accuracy and runtime, this work out-performs the winner of the CAD Contest at ICCAD 2016 in terms of contest scoring measure.

Original languageEnglish
Title of host publication2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538642603
DOIs
StatePublished - 5 Jun 2018
Event2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan
Duration: 16 Apr 201819 Apr 2018

Publication series

Name2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Conference

Conference2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
CountryTaiwan
CityHsinchu
Period16/04/1819/04/18

Keywords

  • MapReduce
  • Prüfer encoding
  • design for manufacturability
  • pattern classification

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