Device aging, which causes significant loss on circuit performance and lifetime, has been a primary factor in reliability degradation of nanoscale designs. In this article, we propose to take advantage of aging-induced clock skews (i.e., make them useful for aging tolerance) by manipulating and recycling these time-varying skews to compensate for the performance degradation of logic networks. The goal is to assign achievable/reasonable aging-induced clock skews in a circuit, such that its effective performance degradation due to aging can be tolerated. On average, 21.21% aging tolerance can be achieved with insignificant design overhead. Moreover, we employVth assignment on clock buffers to further tolerate the aging-induced degradation of logic networks. WhenVth assignment is applied on top of aforementioned aging manipulation, the average aging tolerance can be enhanced to 29.15%.
|Journal||ACM Transactions on Design Automation of Electronic Systems|
|State||Published - Dec 2019|
- Clock network