Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levels

Ming-Dou Ker*, Wei Jen Chang, Wen Yu Lo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

ESD protection design for mixed-voltage I/O interfaces with the low-voltage-triggered PNP (LVTPNP) devices is proposed in this paper. The LVTPNP, by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the PNP devices, is designed to protect the mixed-voltage I/O pads for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS). The experimental results in a 0.35-μm CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device.

Original languageEnglish
Title of host publicationProceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004
PublisherIEEE Computer Society
Pages433-438
Number of pages6
ISBN (Print)0769520936, 9780769520933
DOIs
StatePublished - 1 Jan 2004
EventProceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004 - San Jose, CA, United States
Duration: 22 Mar 200424 Mar 2004

Publication series

NameProceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Conference

ConferenceProceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004
CountryUnited States
CitySan Jose, CA
Period22/03/0424/03/04

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