Low-voltage low-power IF-baseband digital down converter

Shyh-Jye Jou*, Tsan I. Hsu, C. K. Wang

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

A low-voltage low-power all digital down converter (ADDC) is presented for implementing the IF front end signal processing. The ADDC chip accepts a 5-bits digitized intermediate-frequency (IF) input signal and generates a pair of 10-bits filtered in-phase and quadrature baseband signals. Low power consumption is main design consideration in this ADDC chip. Thus, many low power design technologies that include algorithm, architecture and circuit level are used to keep the power dissipation minimum. The ADDC has a symbol rate of 1.2288 MHz (clock rate 19.6608 MHz) and 1 mW average power dissipation when operated in 2 V power supply. The chip was fabricated in a 0.8 μm single poly double metal CMOS process. The core area is 2.45 mm2 and is composed of 12,100 transistors.

Original languageEnglish
Pages270-274
Number of pages5
DOIs
StatePublished - 1 Jan 1997
EventProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China
Duration: 3 Jun 19975 Jun 1997

Conference

ConferenceProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
CityTaipei, China
Period3/06/975/06/97

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    Jou, S-J., Hsu, T. I., & Wang, C. K. (1997). Low-voltage low-power IF-baseband digital down converter. 270-274. Paper presented at Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications, Taipei, China, . https://doi.org/10.1109/VTSA.1997.614773