A low-voltage low-power all digital down converter (ADDC) is presented for implementing the IF front end signal processing. The ADDC chip accepts a 5-bits digitized intermediate-frequency (IF) input signal and generates a pair of 10-bits filtered in-phase and quadrature baseband signals. Low power consumption is main design consideration in this ADDC chip. Thus, many low power design technologies that include algorithm, architecture and circuit level are used to keep the power dissipation minimum. The ADDC has a symbol rate of 1.2288 MHz (clock rate 19.6608 MHz) and 1 mW average power dissipation when operated in 2 V power supply. The chip was fabricated in a 0.8 μm single poly double metal CMOS process. The core area is 2.45 mm2 and is composed of 12,100 transistors.
|Number of pages||5|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China|
Duration: 3 Jun 1997 → 5 Jun 1997
|Conference||Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications|
|Period||3/06/97 → 5/06/97|