Low-voltage low-power CMOS true-single-phase clocking scheme with locally asynchronous logic circuits

Hong Yi Huang*, Kuo Hsing Cheng, Jinn Shyan Wang, Yuan Hua Chu, Tain Shun Wu, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalConference article

3 Scopus citations

Abstract

New CMOS differential logic circuits, called asynchronous latched CMOS differential logic (ALCDL) circuits, are proposed and analyzed. The ALCDL can implement a complex function in a single gate and achieve high operation speed without dc power dissipation. New CMOS differential latches, which can be used to prevent extra transitions and reduce the power dissipation, are also proposed. A new clocking scheme is designed by locally using the ALCDL circuits and the entire system is synchronized to a single global clock. As compared to the conventional true-single-phase clock system, the loading of the global clock line and transient noise induced by precharge operation can be largely reduced. Simulation results show that the new clocking scheme and logic circuits benefit in high-speed and low-power performances, especially in low supply voltage.

Original languageEnglish
Pages (from-to)1572-1575
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
DOIs
StatePublished - 1 Jan 1995
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: 30 Apr 19953 May 1995

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