Low-voltage high-speed programming/erasing floating-gate memory device with gate-all-around polycrystalline silicon nanowire

Ko Hui Lee, Jung Ruey Tsai, Ruey Dar Chang, Horng-Chih Lin, Tiao Yuan Huang

Research output: Contribution to journalArticle

6 Scopus citations

Abstract

A gate-all-around polycrystalline silicon nanowire (NW) floating-gate (FG) memory device was fabricated and characterized in this work. The cross-section of the NW channels was intentionally made to be triangular in shape in order to study the effects of the corners on the device operation. Our results indicate that the channel corners are effective in lowering the programming and erasing (P/E) operation voltages. As compared with the charge-trapping type devices, a larger memory window is obtained with the FG scheme under low-voltage P/E conditions. A model considering the nature of the charge storage medium is proposed to explain the above findings.

Original languageEnglish
Article number153102
JournalApplied Physics Letters
Volume103
Issue number15
DOIs
StatePublished - 7 Oct 2013

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