Low-voltage green transistor using ultra shallow junction and hetero-tunneling

Anupama Bowonder*, Pratik Patel, Kanghoon Jeon, Jungwoo Oh, Prashant Majhi, Hsing Huang Tseng, Chen-Ming Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

37 Scopus citations

Abstract

A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.

Original languageEnglish
Title of host publicationIWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology
Pages93-96
Number of pages4
DOIs
StatePublished - 8 Sep 2008
EventIWJT-2008 - International Workshop on Junction Technology - Shanghai, China
Duration: 15 May 200816 May 2008

Publication series

NameIWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology

Conference

ConferenceIWJT-2008 - International Workshop on Junction Technology
CountryChina
CityShanghai
Period15/05/0816/05/08

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