Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

Chun Chiang, Ping Chen Chang, Mei Ling Chao, Tien Hao Tang, Kuan Cheng Su, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (VBD) and low holding voltage (Vh) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM<8kV) and good turn-on efficiency (Vt1=8.1V) without suffering from low VBD and latch-up issues.

Original languageEnglish
Title of host publication24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-3
Number of pages3
ISBN (Electronic)9781538617793
DOIs
StatePublished - 5 Oct 2017
Event24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017 - Chengdu, China
Duration: 4 Jul 20177 Jul 2017

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume2017-July

Conference

Conference24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
CountryChina
CityChengdu
Period4/07/177/07/17

Fingerprint Dive into the research topics of 'Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering'. Together they form a unique fingerprint.

  • Cite this

    Chiang, C., Chang, P. C., Chao, M. L., Tang, T. H., Su, K. C., & Ker, M-D. (2017). Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering. In 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017 (pp. 1-3). (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2017-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA.2017.8060226