Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions

S. H. Lin; C. H. Cheng; W. B. Chen; F. S. Yeh; Albert Chin

doi:10.1109/LED.2009.2020307

Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions

S. H. Lin^*, C. H. Cheng, W. B. Chen, F. S. Yeh, Albert Chin

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

We demonstrate a low threshold voltage (V _t ) of -0.17 V and good hole mobility (54 cm ² /V · s at 0.8 MV/cm) in TaN/ Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO ₂ -covered Ni/Ga which reduced the high-κ dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.

Original language	English
Pages (from-to)	681-863
Number of pages	183
Journal	IEEE Electron Device Letters
Volume	30
Issue number	6
DOIs	https://doi.org/10.1109/LED.2009.2020307
State	Published - 18 May 2009

Keywords

LaTiO
Low V
Solid-phase diffusion (SPD)

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title = "Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions",

abstract = " We demonstrate a low threshold voltage (V t ) of -0.17 V and good hole mobility (54 cm 2 /V · s at 0.8 MV/cm) in TaN/ Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO 2 -covered Ni/Ga which reduced the high-κ dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.",

keywords = "LaTiO, Low V, Solid-phase diffusion (SPD)",

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AU - Lin, S. H.

AU - Cheng, C. H.

AU - Chen, W. B.

AU - Yeh, F. S.

AU - Chin, Albert

PY - 2009/5/18

Y1 - 2009/5/18

N2 - We demonstrate a low threshold voltage (V t ) of -0.17 V and good hole mobility (54 cm 2 /V · s at 0.8 MV/cm) in TaN/ Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO 2 -covered Ni/Ga which reduced the high-κ dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.

AB - We demonstrate a low threshold voltage (V t ) of -0.17 V and good hole mobility (54 cm 2 /V · s at 0.8 MV/cm) in TaN/ Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO 2 -covered Ni/Ga which reduced the high-κ dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.

KW - LaTiO

KW - Low V

KW - Solid-phase diffusion (SPD)

UR - http://www.scopus.com/inward/record.url?scp=67649385958&partnerID=8YFLogxK

U2 - 10.1109/LED.2009.2020307

DO - 10.1109/LED.2009.2020307

M3 - Article

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VL - 30

SP - 681

EP - 863

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 6

ER -

Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions

Abstract

Keywords

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