Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions

S. H. Lin*, C. H. Cheng, W. B. Chen, F. S. Yeh, Albert Chin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


We demonstrate a low threshold voltage (V t ) of -0.17 V and good hole mobility (54 cm 2 /V · s at 0.8 MV/cm) in TaN/ Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO 2 -covered Ni/Ga which reduced the high-κ dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.

Original languageEnglish
Pages (from-to)681-863
Number of pages183
JournalIEEE Electron Device Letters
Issue number6
StatePublished - 18 May 2009


  • LaTiO
  • Low V
  • Solid-phase diffusion (SPD)

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