Abstract
We demonstrate a low threshold voltage (V t ) of -0.17 V and good hole mobility (54 cm 2 /V · s at 0.8 MV/cm) in TaN/ Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO 2 -covered Ni/Ga which reduced the high-κ dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.
| Original language | English |
|---|---|
| Pages (from-to) | 681-863 |
| Number of pages | 183 |
| Journal | IEEE Electron Device Letters |
| Volume | 30 |
| Issue number | 6 |
| DOIs | |
| State | Published - 18 May 2009 |
Keywords
- LaTiO
- Low V
- Solid-phase diffusion (SPD)
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Lin, S. H., Cheng, C. H., Chen, W. B., Yeh, F. S., & Chin, A. (2009). Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions. IEEE Electron Device Letters, 30(6), 681-863. https://doi.org/10.1109/LED.2009.2020307