Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer

Huang-Chung Cheng*, Chun Chien Tsai, Jian Hao Lu, Ting Kuo Chang, Ching Wei Lin, Bo Ting Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, location-controlled grain growth with a-Si spacer structure was fabricated. Consequently, High-performance poly-Si TFTs with field-effect mobility exceeding 367 cm 2/V-s and high device uniformity have been fabricated. The excellent electrical characteristics is attributed to large grain and grain boundary elimination in the channel region.

Original languageEnglish
Title of host publicationProceedings of the International Display Manufacturing Conference and Exhibition, IDMC'05
EditorsH.P. David Shieh, F.C. Chen
Pages52-54
Number of pages3
StatePublished - 1 Dec 2005
EventInternational Display Manufacturing Conference and Exhibition, IDMC'05 - Taipei, Japan
Duration: 21 Feb 200524 Feb 2005

Publication series

NameInternational Display Manufacturing Conference and Exhibition, IDMC'05

Conference

ConferenceInternational Display Manufacturing Conference and Exhibition, IDMC'05
CountryJapan
CityTaipei
Period21/02/0524/02/05

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