Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer

Huang-Chung Cheng; Chun Chien Tsai; Jian Hao Lu; Ting Kuo Chang; Ching Wei Lin; Bo Ting Chen

Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer

Huang-Chung Cheng^*, Chun Chien Tsai, Jian Hao Lu, Ting Kuo Chang, Ching Wei Lin, Bo Ting Chen

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, location-controlled grain growth with a-Si spacer structure was fabricated. Consequently, High-performance poly-Si TFTs with field-effect mobility exceeding 367 cm ²/V-s and high device uniformity have been fabricated. The excellent electrical characteristics is attributed to large grain and grain boundary elimination in the channel region.

Original language	English
Title of host publication	Proceedings of the International Display Manufacturing Conference and Exhibition, IDMC'05
Editors	H.P. David Shieh, F.C. Chen
Pages	52-54
Number of pages	3
State	Published - 1 Dec 2005
Event	International Display Manufacturing Conference and Exhibition, IDMC'05 - Taipei, Japan Duration: 21 Feb 2005 → 24 Feb 2005

Publication series

Name	International Display Manufacturing Conference and Exhibition, IDMC'05

Conference

Conference	International Display Manufacturing Conference and Exhibition, IDMC'05
Country	Japan
City	Taipei
Period	21/02/05 → 24/02/05

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Cheng, H-C., Tsai, C. C., Lu, J. H., Chang, T. K., Lin, C. W., & Chen, B. T. (2005). Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer. In H. P. David Shieh, & F. C. Chen (Eds.), Proceedings of the International Display Manufacturing Conference and Exhibition, IDMC'05 (pp. 52-54). (International Display Manufacturing Conference and Exhibition, IDMC'05).

Cheng, Huang-Chung ; Tsai, Chun Chien ; Lu, Jian Hao ; Chang, Ting Kuo ; Lin, Ching Wei ; Chen, Bo Ting. / Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer. Proceedings of the International Display Manufacturing Conference and Exhibition, IDMC'05. editor / H.P. David Shieh ; F.C. Chen. 2005. pp. 52-54 (International Display Manufacturing Conference and Exhibition, IDMC'05).

@inproceedings{3252e1ffad9143328402717ce4584bba,

title = "Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer",

abstract = "In this paper, location-controlled grain growth with a-Si spacer structure was fabricated. Consequently, High-performance poly-Si TFTs with field-effect mobility exceeding 367 cm 2/V-s and high device uniformity have been fabricated. The excellent electrical characteristics is attributed to large grain and grain boundary elimination in the channel region.",

author = "Huang-Chung Cheng and Tsai, {Chun Chien} and Lu, {Jian Hao} and Chang, {Ting Kuo} and Lin, {Ching Wei} and Chen, {Bo Ting}",

year = "2005",

month = dec,

day = "1",

language = "English",

isbn = "9572852221",

series = "International Display Manufacturing Conference and Exhibition, IDMC'05",

pages = "52--54",

editor = "{David Shieh}, H.P. and F.C. Chen",

booktitle = "Proceedings of the International Display Manufacturing Conference and Exhibition, IDMC'05",

note = "null ; Conference date: 21-02-2005 Through 24-02-2005",

}

Cheng, H-C, Tsai, CC, Lu, JH, Chang, TK, Lin, CW & Chen, BT 2005, Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer. in HP David Shieh & FC Chen (eds), Proceedings of the International Display Manufacturing Conference and Exhibition, IDMC'05. International Display Manufacturing Conference and Exhibition, IDMC'05, pp. 52-54, International Display Manufacturing Conference and Exhibition, IDMC'05, Taipei, Japan, 21/02/05.

Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer. / Cheng, Huang-Chung; Tsai, Chun Chien; Lu, Jian Hao; Chang, Ting Kuo; Lin, Ching Wei; Chen, Bo Ting.

Proceedings of the International Display Manufacturing Conference and Exhibition, IDMC'05. ed. / H.P. David Shieh; F.C. Chen. 2005. p. 52-54 (International Display Manufacturing Conference and Exhibition, IDMC'05).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer

AU - Cheng, Huang-Chung

AU - Tsai, Chun Chien

AU - Lu, Jian Hao

AU - Chang, Ting Kuo

AU - Lin, Ching Wei

AU - Chen, Bo Ting

PY - 2005/12/1

Y1 - 2005/12/1

N2 - In this paper, location-controlled grain growth with a-Si spacer structure was fabricated. Consequently, High-performance poly-Si TFTs with field-effect mobility exceeding 367 cm 2/V-s and high device uniformity have been fabricated. The excellent electrical characteristics is attributed to large grain and grain boundary elimination in the channel region.

AB - In this paper, location-controlled grain growth with a-Si spacer structure was fabricated. Consequently, High-performance poly-Si TFTs with field-effect mobility exceeding 367 cm 2/V-s and high device uniformity have been fabricated. The excellent electrical characteristics is attributed to large grain and grain boundary elimination in the channel region.

UR - http://www.scopus.com/inward/record.url?scp=33644642436&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33644642436

SN - 9572852221

SN - 9789572852224

T3 - International Display Manufacturing Conference and Exhibition, IDMC'05

SP - 52

EP - 54

BT - Proceedings of the International Display Manufacturing Conference and Exhibition, IDMC'05

A2 - David Shieh, H.P.

A2 - Chen, F.C.

Y2 - 21 February 2005 through 24 February 2005

ER -

Cheng H-C, Tsai CC, Lu JH, Chang TK, Lin CW, Chen BT. Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer. In David Shieh HP, Chen FC, editors, Proceedings of the International Display Manufacturing Conference and Exhibition, IDMC'05. 2005. p. 52-54. (International Display Manufacturing Conference and Exhibition, IDMC'05).