Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique

Chun Jung Su, Tzu I. Tsai, Horng-Chih Lin*, Tiao Yuan Huang, Tien-Sheng Chao

*Corresponding author for this work

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

In this work, we present a gate-all-around (GAA) low-temperature poly-Si nanowire (NW) junctionless device with TiN/Al2O3 gate stack using an implant-free approach. Since the source/drain and channel regions are sharing one in situ phosphorous-doped poly-Si material, the process flow and cost could be efficiently reduced. Owing to the GAA configuration and small volume of NW channels, the fabricated devices with heavily doped channels display superior switching behaviors and excellent immunity to short-channel effects. Besides, the negative fixed charges in Al2O3 are found to be helpful to obtain desirable positive threshold voltages for the n+-poly-Si channel devices. Thus, the simple and low-cost fabrication method along with excellent device characteristics makes the proposed GAA NW transistor a promising candidate for future 3-D electronics and system-on-panel applications.

Original languageEnglish
Pages (from-to)1-14
Number of pages14
JournalNanoscale Research Letters
Volume7
DOIs
StatePublished - 24 Jul 2012

Keywords

  • Accumulation mode
  • Gate-all-around
  • Junctionless
  • Low-temperature poly-Si
  • Nanowire

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