Introduction Future CMOS devices require metal-gatehigh-K gate stacks, advanced sourceidrain engineering, and the use of UTB-SO1 [1-3]. The series resistance of shallow sourceidrain junction is a serious issue for future scaling, and Schottky barrier SiD (SSD) structure has been suggested as a potential solution [4-7]. MOSFETs with SSD (SSDT) have been reported using SiO22/ poly-Si gate stack . However, SSDT is particularly attractive for metal gate/high-K gate stack as it avoids the use of high temperature annealing process required for implanted S/D junctions, hence eliminating the thermal stability issues associated with high-K gate stack . In this work, we successfully demonstrate bulk SSDTs with CVD Hf02 high-K dielectric, PVD HfN/TaN metal gate and P'tSi (for PMOS) and DySi2-x(for NMOS) silicide source/drain using a low temperature process. The highest temperature is 420°C after high-K gate stack formation. The process can be easily extended to UTB-SOI structures.