Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration

Yu San Chien*, Yan Pin Huang, Ruoh Ning Tzeng, Ming Shaw Shy, Teu Hua Lin, Kou Hua Chen, Ching Te Chuang, Wei Hwang, Jin-Chern Chiou, Chi Tsung Chiu, Ho Ming Tong, Kuan-Neng Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

Two bonded structures, Cu/In bonding and Cu-Cu bonding with Ti passivation, were investigated for the application of 3D interconnects. For Cu/In bonding, the bonds were achieved at 170°C due to the isothermal solidification. The intermetallic compounds formed in the joint was Cu2In phase. For another case, Cu-Cu bonding with Ti passivation was successfully achieved at 180°C Application of Ti passivation can protect inner Cu from oxidation; therefore, the required bonding temperature can be decreased. Compared to direct Cu-Cu bonding, Cu/In bonding and Cu-Cu bonding with Ti passivation can be performed at low temperature, which can meet low thermal budget requirement for most devices. Besides, with the good electrical performance and reliability, these two bonded interconnects can be applied for 3D IC interconnects.

Original languageEnglish
Title of host publication2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
PublisherIEEE
Pages1146-1152
Number of pages7
ISBN (Print)9781479902330
DOIs
StatePublished - 9 Sep 2013
Event2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013 - Las Vegas, NV, United States
Duration: 28 May 201331 May 2013

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503

Conference

Conference2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
CountryUnited States
CityLas Vegas, NV
Period28/05/1331/05/13

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