Low-temperature direct wafer bonding for III-V compound semiconductors to nanometer-scale grating arrays

Bai Ci Chen, Yu Chang Wu, Jen Hung Huang, Hao-Chung Kuo, Chien-Chung Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we designed the grating with different periodicities on silicon. Aluminum or silicon dioxide would be filled in the inter-space of grating. Besides, the surface reflectivity of different structures was measured and the theoretical calculation was performed. By oxygen plasma-enhanced process, we successfully present the results of a low-temperature process for direct bonding of InP epitaxial layers on a silicon wafer.

Original languageEnglish
Title of host publication4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479942084
DOIs
StatePublished - 23 Jun 2015
Event4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015 - Taipei, Taiwan
Duration: 4 May 20156 May 2015

Publication series

Name4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015

Conference

Conference4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015
CountryTaiwan
CityTaipei
Period4/05/156/05/15

Keywords

  • FDTD simulation
  • Grating
  • Surface reflectivity
  • Wafer bonding

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  • Cite this

    Chen, B. C., Wu, Y. C., Huang, J. H., Kuo, H-C., & Lin, C-C. (2015). Low-temperature direct wafer bonding for III-V compound semiconductors to nanometer-scale grating arrays. In 4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015 [7132038] (4th International Symposium on Next-Generation Electronics, IEEE ISNE 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISNE.2015.7132038